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? semiconductor components industries, llc, 2001 december, 2001 rev. 1 1 publication order number: ncp1411/d ncp1411 sync-rect pfm step-up dc-dc converter with low-battery detector and ring-killer ncp1411 is a monolithic micropower high frequency boost (stepup) voltage switching converter ic specially designed for battery operated handheld electronic products up to 250 ma loading. it integrates synchronous rectifier for improving efficiency as well as eliminating the external schottky diode. high switching frequency (up to 600 khz) allows low profile inductor and output capacitor being used. lowbattery detector, logiccontrolled shutdown and cyclebycycle current limit provide valueadded features for various batteryoperated applications. the innovative ringkiller circuitry guarantees quiet operation in discontinuous conduction mode. with all these functions on, the device quiescent supply current is only 9.0 a typical. this device is available in the space saving compact micro8 package. features ? high efficiency, up to 92% ? very low device quiescent supply current of 9.0 a typical ? builtin synchronous rectifier (pfet) eliminates one external schottky diode ? high switching frequency (up to 600 khz) allows use of small size inductor ? high accuracy reference output, 1.19 v 0.6% @ 25 c, can supply more than 2.5 ma when v out 3.3 v ? ringkiller for quiet operation in discontinuous conduction mode ? 1.0 v startup at no load guaranteed ? output voltage from 1.5 v to 5.5 v adjustable ? output current up to 250 ma @ v in = 2.5 v, v out = 3.3 v ? logiccontrolled shutdown ? open drain lowbattery detector output ? 1.0 a cycle by cycle current limit ? low profile and minimum external parts ? compact micro8 package typical applications ? personal digital assistant (pda) ? handheld digital audio product ? camcorder and digital still camera ? handheld instrument ? conversion from one or two nimh or nicd, or one liion cell to 3.3 v/5.0 v http://onsemi.com ordering information micro8 dm suffix case 846a 1 8 pin connections a2 = device marking a = assembly location y = year w = wafer lot (top view) marking diagram a2 ayw 1 fb 8 out 2 lbi/en 3 lbo 4 ref 7 lx 6 gnd 5 bat device package shipping NCP1411Dmr2 micro8 4000 tape & reel
ncp1411 http://onsemi.com 2 figure 1. typical operating circuit fb lbi/en lbo ref out lx gnd bat 4 3 2 1 5 6 7 8 150 nf 33 f ncp1411 + 350 k 10 f 22 h 220 pf 150 pf 200 k c en 120 nf output 1.5 to 5.5 v i out typical up to 250 ma at 3.3 v output and 2.5 v input input 1 v to v out low battery sense input shutdown open drain input low battery open drain output r lb1 r lb2 pin function description pin # symbol pin description 1 fb output voltage feedback input. 2 lbi/en lowbattery detector input and ic enable. 3 lbo opendrain lowbattery detector output. output is low when v lbi is < 1.178 v. lbo is high impedance during shutdown. 4 ref 1.190 v reference voltage output, bypassing with 150 nf capacitor if this pin is not loaded, bypassing with 1.0 f if this pin is loaded up to 2.5 ma @ v out = 3.3 v. 5 bat battery input connection for internal ringkiller. 6 gnd ground. 7 lx nchannel and pchannel power mosfet drain connection. 8 out power output. out also provides bootstrapped power to the device. maximum ratings rating symbol value unit device power supply (pin 8) v out 0.3 to 6.0 v input/output pins pins 15, pin 7 v io 0.3 to 6.0 v thermal characteristics micro8 plastic package maximum power dissipation @ t a = 25 c thermal resistance, junctiontoair p d r q ja 520 240 mw c/w operating junction temperature range t j 40 to +150 c operating ambient temperature range t a 40 to +85 c storage temperature range t stg 55 to +150 c 1. this device contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22a114. machine model (mm) 200 v per jedec standard: jesd22a115. 2. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja 3. latchup current maximum rating: 150 ma per jedec standard: jesd78. 4. moisture sensitivity level: msl 1 per ipc/jedec standard: jstd020a.
ncp1411 http://onsemi.com 3 electrical characteristics (v out = 3.3 v, t a = 25 c for typical value, 40 c t a 85 c for min/max values unless otherwise noted.) characteristic symbol min typ max unit operating input voltage v in 1.0 5.5 v output voltage range (adjusted by external feedback) v out v in 5.5 v reference voltage (c ref = 150 nf, under no loading, t a = 25 c) v ref_nl 1.183 1.190 1.197 v reference voltage (c ref = 150 nf, under no loading, 40 c t a 85 c) v ref_nl_a 1.178 1.202 v reference voltage temperature coefficient tc vref 0.03 mv/ c reference voltage load current (v out = 3.3 v, v ref = v ref_nl 1.5%, c ref = 1.0 f) (note 5) i ref 2.5 ma reference voltage load regulation (v out = 3.3 v, i load = 0 to 100 a, c ref = 1.0 f) v ref_load 0.015 1.0 mv reference voltage line regulation (v out from 1.5 v to 5.5 v, c ref = 1.0 f) v ref_line 0.03 1.0 mv/v fb, lbi input threshold (i load = 0 ma) v fb, v lbi 1.174 1.190 1.200 v nfet on resistance r ds(on)n 0.6 w pfet on resistance r ds(on)p 0.9 w lx switch current limit (nfet) i lim 1.0 a operating current into out (v fb = 1.4 v, i.e. no switching, v out = 3.3 v) i q 9.0 14 a shutdown current into out (lbi/en = gnd) i sd 0.05 1.0 a lx switch max. ontime (v fb = 1.0 v, v out = 3.3 v) t on 1.2 1.4 1.8 s lx switch min. offtime (v fb = 1.0 v, v out = 3.3 v) t off 0.25 0.31 0.37 s fb input current i fb 1.5 9.0 na shutdown current into bat (lbi/en = 0 v, v out = v bat = 3.0 v) i lbt 50 na bat to lx resistance (v fb = 1.4 v, v out = 3.3 v) r lbt_lx 100 w lbi/en input current i lbi/en 1.5 8.0 na lbo low output voltage (v lbi = 0 v, i sink = 1.0 ma) v lbo_l 0.05 v enable (pin 2) input threshold, low v en 0.3 v enable (pin 2) input threshold, high v en 0.6 v 5. loading capability increases with v out .
ncp1411 http://onsemi.com 4 figure 2. simplified functional diagram chip enable voltage reference - + - + pfm - + - + 20 mv gnd gnd gnd v dd v dd m1 gnd ilim _ilim 1 4 2 zlc _v refok _pfm _cen _pwqonce _zcur _mson _mainsw2on _synsw2on control logic v dd v out fb ref lbi/en v bat _mainswofd m3 _synswofd 5 7 8 6 3 bat lx out lbo m2 sensefet gnd r sense + +
ncp1411 http://onsemi.com 5 typical operating characteristics figure 3. reference voltage versus output current 1 10 1000 100 1.220 1.190 1.200 v ref , reference voltage (v) i load , output current (ma) 1.195 1.205 1.210 1.215 figure 4. reference voltage versus input voltage at out pin 12 6 4 1.195 1.180 1.186 v ref , reference voltage (v) v out , input voltage at out pin (v) 1.183 1.189 1.192 figure 5. reference voltage versus temperature 40 0 100 20 1.194 1.184 v ref , reference voltage (v) t a , ambient temperature ( c) 1.186 1.188 1.190 1.192 figure 6. switch on resistance versus temperature 40 0 100 20 1.5 0 0.6 r ds(on) , switch on resistance ( ) t a , ambient temperature ( c) 0.3 0.9 1.2 figure 7. l x switch max. on time versus temperature 40 0 100 40 1.8 1.2 1.4 l x , switch max. on time (t on / s) t a , ambient temperature ( c) 1.3 1.5 1.6 1.7 0 20 120 100 1.9 0.6 1.1 v batt , min. startup battery voltage (v) i load , output loading current (ma) 0.9 1.4 1.6 figure 8. min. startup battery voltage versus loading current 35 20 40 60 80 v out = 3.3 v l = 22 h c in = 10 f c out = 33 f c ref = 1 f t a = 25 c v in = 1.8 v v in = 2.2 v v in = 3.0 v c ref = 1 f t a = 25 c i ref = 2.5 ma i ref = 0 ma v out = 3.3 v c ref = 150 nf i ref = 0 ma 20 40 60 80 v out = 3.3 v pfet (m2) nfet (m1) 20 20 80 60 40 60 80 without schottky diode with schottky diode (mbr0502)
ncp1411 http://onsemi.com 6 figure 9. efficiency versus load current 1 10 1000 100 100 50 70 efficiency (%) i load , output loading current (ma) 60 80 90 figure 10. efficiency versus load current figure 11. efficiency versus load current figure 12. efficiency versus load current figure 13. efficiency versus load current figure 14. efficiency versus load current v in = 1.8 v v out = 3.3 v c in = 10 f c out = 33 f l = 22 h l = 10 h l = 15 h 1 10 1000 100 100 50 70 efficiency (%) i load , output loading current (ma) 60 80 90 v in = 2.2 v v out = 5 v c in = 10 f c out = 33 f l = 22 h l = 27 h 1 10 1000 100 100 efficiency (%) i load , output loading current (ma) v in = 2.2 v v out = 3.3 v c in = 10 f c out = 33 f l = 22 h l = 10 h l = 15 h 1 10 1000 100 100 50 70 efficiency (%) i load , output loading current (ma) 60 80 90 l = 22 h l = 27 h 50 70 60 80 90 1 10 1000 100 100 efficiency (%) i load , output loading current (ma) v in = 3 v v out = 3.3 v c in = 10 f c out = 33 f l = 22 h l = 10 h l = 15 h 1 10 1000 100 100 50 70 efficiency (%) i load , output loading current (ma) 60 80 90 v in = 4.5 v v out = 5 v c in = 10 f c out = 33 f l = 22 h l = 27 h 50 70 60 80 90 v in = 2.2 v v out = 3.3 v c in = 10 f c out = 33 f
ncp1411 http://onsemi.com 7 figure 15. output voltage change versus load current 1 10 1000 100 3.0 3.0 1.0 output voltage change (%) i load , output loading current (ma) 2.0 1.0 2.0 figure 16. output voltage change versus load current figure 17. battery input voltage vesus output ripple voltage figure 18. battery input voltage versus output ripple voltage figure 19. no load operating current versus input voltage at out pin figure 20. startup transient response l = 22 h v out = 3.3 v c in = 10 f c out = 33 f v in = 1.8 v 1 1.5 3 2 200 v ripple , ripple voltage (mv pp ) v batt , battery input voltage (v) v out = 3.3 v c in = 10 f c out = 33 f l = 22 h 100 ma 0 80 40 120 160 023 20 i batt , no load operating current ( a) v out , input voltage at out pin (v) 0 8 4 12 16 156 47 2.5 200 ma 1 1.5 3 2 200 v ripple , ripple voltage (mv pp ) v batt , battery input voltage (v) v out = 3.3 v c in = 10 f c out = 33 f l = 15 h 100 ma 0 80 40 120 160 2.5 200 ma 0 3 v 2.2 v 1 10 1000 100 3.0 3.0 1.0 output voltage change (%) i load , output loading current (ma) 2.0 1.0 2.0 l = 15 h v out = 3.3 v c in = 10 f c out = 33 f 0 3 v 2.2 v (v in = 2.2 v, v out = 3.3 v, i load = 100 ma; l = 22 m h, c out = 33 m f) upper trace: output voltage waveform, 2.0 v/division lower trace: shutdown pin waveform, 1.0 v/division v in = 1.8 v
ncp1411 http://onsemi.com 8 figure 21. continuous conduction mode switching waveform figure 22. discontinuous conduction mode switching waveform figure 23. line transient response for v out = 3.3 v figure 24. load transient response for v in = 1.8 v figure 25. load transient response for v in = 2.4 v figure 26. load transient response for v in = 3.3 v (v in = 2.2 v, v out = 3.3 v, i load = 100 ma; l = 22 m h, c out = 33 m f) upper trace: voltage at l x pin, 2.0 v/division middletrace: output voltage ripple, 50 mv/division lower trace: inductor current, i l , 100 ma/division (v in = 2.2 v, v out = 3.3 v, i load = 30 ma; l = 22 m h, c out = 33 m f) upper trace: voltage at l x pin, 2.0 v/division middletrace: output voltage ripple, 50 mv/division lower trace: inductor current, i l , 100 ma/division (v in = 1.8 v to 3.0 v, l = 22 m h, c out = 33 m f) upper trace: output voltage ripple, 100 mv/division lower trace: battery voltage, v in , 1.0 v/division (v out = 3.3 v, i load = 10 ma to 100 ma; l = 22 m h, c out = 33 m f) upper trace: output voltage ripple, 100 mv/division lower trace: load current, i load , 50 ma/division (v out = 3.3 v, i load = 10 ma to 100 ma; l = 22 m h, c out = 33 m f) upper trace: output voltage ripple, 100 mv/division lower trace: load current, i load , 50 ma/division (v out = 3.3 v, i load = 10 ma to 100 ma; l = 22 m h, c out = 33 m f) upper trace: output voltage ripple, 100 mv/division lower trace: load current, i load , 50 ma/division
ncp1411 http://onsemi.com 9 detailed operation descriptions ncp1411 is a monolithic micropower high frequency stepup voltage switching converter ic specially designed for battery operated handheld electronic products up to 250 ma loading. it integrates synchronous rectifier for improving efficiency as well as eliminating the external schottky diode. high switching frequency (up to 600 khz) allows low profile inductor and output capacitor being used. lowbattery detector, logiccontrolled shutdown and cyclebycycle current limit provide valueadded features for various batteryoperated application. with all these functions on, the quiescent supply current is only 9.0 a typical. this device is available in a compact micro8 package. pfm regulation scheme from the simplified functional diagram (figure 2), the output voltage is divided down and fed back to pin 1 (fb). this voltage goes to the noninverting input of the pfm comparator whereas the comparator's inverting input is connected to ref. a switching cycle is initiated by the falling edge of the comparator, at the moment, the main switch (m1) is turned on. after the maximum ontime (typical 1.4 s) elapses or the current limit is reached, m1 is turned off, and the synchronous switch (m2) is turned on. the m1 off time is not less than the minimum offtime (typical 0.31 s), this is to ensure energy transfer from the inductor to the output capacitor. if the regulator is operating at continuous conduction mode (ccm), m2 is turned off just before m1 is supposed to be on again. if the regulator is operating at discontinuous conduction mode (dcm), which means the coil current will decrease to zero before the next cycle, m1 is turned off as the coil current is almost reaching zero. the comparator (zlc) with fixed offset is dedicated to sense the voltage drop across m2 as it is conducting, when the voltage drop is below the offset, the zlc comparator output goes high, and m2 is turned off. negative feedback of closed loop operation regulates voltage at pin 1 (fb) equal to the internal voltage reference (1.190 v). synchronous rectification synchronous rectifier is used to replace schottky diode for eliminating the conduction loss contributed by forward voltage of the latter. synchronous rectifier is normally realized by powerfet with gate control circuitry which, however, involved relative complicated timing concerns. as main switch m1 is being turned off, if the synchronous switch m2 is just turned on with m1 not being completed turned off, current will be shunt from the output bulk capacitor through m2 and m1 to ground. this power loss lowers overall efficiency. so a certain amount of dead time is introduced to make sure m1 is completely off before m2 is being turned on. when the main regulator is operating in ccm, as m2 is being turned off, and m1 is just turned on with m2 not being completely turned off, the above mentioned situation will occur. so dead time is introduced to make sure m2 is completely turned off before m1 is being turned on. when the regulator is operating in dcm, as coil current is dropped to zero, m2 is supposed to be off. fail to do so, reverse current will flow from the output bulk capacitor through m2 and then the inductor to the battery input. it causes damage to the battery. so the zlc comparator comes with fixed offset voltage to switch m2 off before any reverse current builds up. however, if m2 is switch off too early, large residue coil current flows through the body diode of m2 and increases conduction loss. therefore, determination on the offset voltage is essential for optimum performance. with the implementation of synchronous rectification, efficiency can be as high as 92%. for single cell input voltage, use an external schottky diode such as mbr0520 connected from pin 7 to pin 8 to ensure quick startup. ringkiller when the device entered discontinuous conduction mode operation, a typical ringing at lx pin will start while the inductor current just ceased. this ringing is caused primarily by the capacitance and inductance at lx node and the result can produce unwanted emi problem to the system. in order to eliminate this ringing, an internal damping switch (m3) is implemented to provide a low impedance path to dissipate the residue energy stored in the inductor once the operation entered the discontinuous conduction mode. this feature can improve the emi problem. the performance of the ringkiller switch is shown in figure 22. cyclebycycle current limit from figure 2, sensefet is applied to sample the coil current as m1 is on. with that sample current flowing through a sense resistor, sensevoltage is developed. threshold detector (ilim) detects whether the sensevoltage is higher than preset level. if it happens, detector output signifies the control logic to switch off m1, and m1 can only be switched on as next cycle starts after the minimum offtime (typical 0.31 s). with properly sizing of sensefet and sense resistor, the peak coil current limit is set at 1.0 a typically. voltage reference the voltage at ref is set typically at +1.190 v. it can deliver up to 2.5 ma with load regulation 1.5%, at v out equal to 3.3 v. if v out is increased, the ref load capability can also be increased. a bypass capacitor of 0.15 f is required for proper operation when ref is not loaded. if ref is loaded, 1.0 f capacitor at ref is needed. shutdown the ic will shutdown when the voltage at pin 2 (lbi/en) is pulled lower than 0.3 v. during shutdown, m1 and m2 are both switched off, however, the body diode of m2 allows current flow from battery to the output, the ic internal circuit will consume less than 0.05 a current typically. if the pin
ncp1411 http://onsemi.com 10 1 voltage raised higher than 0.6 v, the ic will be enabled. the internal circuit will only consume 9.0 a current typically from the out pin. in order to ensure proper startup, a timing capacitor c en as shown in figure 1 is required to provide the reset pulse during batteries are plugged in. the product of r lb1 and c en must be lar ger than 28 msec. lowbattery detection a comparator with 30 mv hysteresis is applied to perform the lowbattery detection function. when pin 2 (lbi/en) is at a voltage, which can be defined by a resistor divider from the battery voltage, lower than the internal reference voltage, 1.190 v, the comparator output will cause a 50 ohm low side switch to be turned on. it will pull down the voltage at pin 3 (lbo) which has a hundreds kiloohm of pullhigh resistance. if the pin 2 voltage is higher than 1.190 v +30 mv, the comparator output will cause the 50 ohm low side switch to be turned off, pin 3 will become high impedance, and its voltage will be pulled high. applications information output voltage setting the output voltage of the converter is determined by the external feedback network comprised of r fb1 and r fb2 and the relationship is given by: v out 1.190 v 1 r fb1 r fb2 where r fb1 and r fb2 are the upper and lower feedback resistors respectively. low battery detect level setting the low battery detect voltage of the converter is determined by the external divider network comprised of r lb1 and r lb2 and the relationship is given by: v lb 1.190 v 1 r lb1 r lb2 where r lb1 and r lb2 are the upper and lower divider resistors respectively. inductor selection the ncp1411 is tested to produce optimum performance with a 22 h inductor at v in = 3.0 v, v out = 3.3 v supplying output current up to 250 ma. for other input/output requirements, inductance in the range 10 h to 47 h can be used according to end application specifications. selecting an inductor is a compromise between output current capability and tolerable output voltage ripple. of course, the first thing we need to obey is to keep the peak inductor current below its saturation limit at maximum current and the i lim of the device. in ncp1411, i lim is set at 1.0 a. as a rule of thumb, low inductance values supply higher output current, but also increase the ripple at output and reducing efficiency, on the other hand, high inductance values can improve output ripple and efficiency, however it also limit the output current capability at the same time. one other parameter of the inductor is its dc resistance, this resistance can introduce unwanted power loss and hence reduce overall efficiency, the basic rule is selecting an inductor with lowest dc resistance within the board space limitation of the end application. capacitors selection in all switching mode boost converter applications, both the input and output terminals sees impulsive voltage/current waveforms. the currents flowing into and out of the capacitors multiplying with the equivalent series resistance (esr) of the capacitor producing ripple voltage at the terminals. during the synrect switch off cycle, the charges stored in the output capacitor is used to sustain the output load current. load current at this period and the esr combined and reflected as ripple at the output terminal. for all cases, the lower the capacitor esr, the lower the ripple voltage at output. as a general guide line, low esr capacitors should be used. ceramic capacitors have the lowest esr, but low esr tantalum capacitors can also be used as a cost effective substitute. optional startup schottky diode for low battery voltage in general operation, no external schottky diode is required, however, in case you are intended to operate the device close to 1.0 v level, a schottky diode connected between the lx and out pins as shown in figure 27 can help during startup of the converter. the effect of the additional schottky was shown in figure 8. figure 27. pcb layout recommendations out l x ncp1411 c out l mbr0502 v out pcb layout recommendations good pcb layout plays an important role in switching mode power conversion. careful pcb layout can help to minimize ground bounce, emi noise and unwanted feedback that can affect the performance of the converter. hints suggested in below can be used as a guide line in most situations. grounding starground connection should be used to connect the output power return ground, the input power return ground and the device power ground together at one point. all high
ncp1411 http://onsemi.com 11 current running paths must be thick enough for current flowing through and producing insignificant voltage drop along the path. feedback signal path must be separated with the main current path and sensing directly at the anode of the output capacitor. components placement power components, i.e. input capacitor, inductor and output capacitor, must be placed as close together as possible. all connecting traces must be short, direct and thick. high current flowing and switching paths must be kept away from the feedback (fb, pin 1) terminal to avoid unwanted injection of noise into the feedback path. feedback network feedback of the output voltage must be a separate trace detached from the power path. external feedback network must be placed very close to the feedback (fb, pin 1) pin and sensing the output voltage directly at the anode of the output capacitor. c en 120 nf figure 28. typical application schematic for 2 alkaline cells supply fb lbi/en lbo ref out lx gnd bat 4 3 2 1 5 6 7 8 c ref 150 nf v batt + r fb1 335 k c fb1 150 pf r lb1 225 k gnd c in 10 f/10 v c out 33 f/10 v v out gnd r lb2 330 k r fb2 200 k c fb2 220 pf ncp1411 l + 22 h
ncp1411 http://onsemi.com 12 general design procedures switching mode converter design is considered as black magic to most engineers, some complicate empirical formulae are available for reference usage. those formulae are derived from the assumption that the key components, i.e. power inductor and capacitors are available with no tolerance. practically, its not true, the result is not a matter of how accurate the equations you are using to calculate the component values, the outcome is still somehow away from the optimum point. in below a simple method base on the most basic first order equations to estimate the inductor and capacitor values for ncp1411 operate in continuous conduction mode is introduced. the component value set can be used as a starting point to fine tune the circuit operation. by all means, detail bench testing is needed to get the best performance out of the circuit. design parameters: v in = 1.8 v to 3.0 v, typical 2.4 v v out = 3.3 v i out = 200 ma (250 ma max) v lb = 2.0 v v outripple = 40 mv pp at i out = 250 ma calculate the feedback network: select r fb2 = 200 k r fb1 r fb2 v out v ref 1 r fb1 200 k 3.3 v 1.19 v 1 355 k with the feedback resistor divider, additional small capacitor, c fb1 in parallel with r fb1 is required to ensure stability. the value can be in between 68 pf to 220 pf, the rule is to select the lowest capacitance to ensure stability. also a small capacitor, c fb2 in parallel with r fb2 may also be needed to lower the feedback ripple hence improve output regulation. the use of c fb2 is a compromise between output ripple level and regulation, so careful selection of the value according to end application requirement is needed. in this example, values for c fb1 and c fb2 are 150 pf and 220 pf respectively. calculate the low battery detect divider: v lb = 2.0 v select r lb2 = 330 k r lb1 r lb2 v lb v ref 1 r lb1 330 k 2.0 v 1.19 v 1 225 k c en 28 msec 225 k 120 nf determine the steady state duty ratio, d for typical v in , operation will be optimized around this point: v out v in 1 1 d d 1 v in v out 1 2.4 v 3.3 v 0.273 determine the average inductor current, i lavg at maximum i out : i lavg i out 1 d 250 ma 1 0.273 344 ma determine the peak inductor ripple current, i ripplep and calculate the inductor value: assume i ripplep is 20% of i lavg , the inductance of the power inductor can be calculated as in below: i ripplep = 0.20 x 344 ma = 68.8 ma l v in t on 2i ripplep 2.4 v 1.4 s 2(68.8 ma) 24.4 h standard value of 22 h is selected for initial trial. determine the output voltage ripple, v outripple and calculate the output capacitor value: v outripple = 40 mv pp at i out = 250 ma c out i out t on v out ripple i out esr cout where t on = 1.4 s and esr cout = 0.1 w , c out 250 ma 1.4 s 40 mv 250 ma 0.1 23.33 f from above calculation, we need at least 23.33 f in order to achieve the specified ripple level at conditions stated. practically, a one level larger capacitor will be used to accommodate factors not take into account in the calculation. so a capacitor value of 33 f is selected.
ncp1411 http://onsemi.com 13 package dimensions micro8 dm suffix case 846a02 issue e s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c --- 1.10 --- 0.043 d 0.25 0.40 0.010 0.016 g 0.65 bsc 0.026 bsc h 0.05 0.15 0.002 0.006 j 0.13 0.23 0.005 0.009 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. b a d k g pin 1 id 8 pl 0.038 (0.0015) t seating plane c h j l
ncp1411 http://onsemi.com 14 notes
ncp1411 http://onsemi.com 15 notes
ncp1411 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncp1411/d micro8 is a trademark of international rectifier. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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